This is my newest project that I started in early September 2009. I wanted to know how a cpu works on the gate level so, I decided to build one myself! I used Donn's TTL Computer Processor project to help me understand the concepts. For more details about the computer and my progress, visit my blog page. It is not built yet but my design has been sucessfully simulated. Updated December 2009.
Here are the current specs:
Currently implemented instructions:
Note: All instructions have been tested in the simulator.
I've sucessfully simulated my TTL processor design! Here's a screenshot of the display page (there are actually 10 pages total). In the screenshot it is running at 10Hz but it can be simulated up to 500Hz (or until it takes too much cpu on my desktop). It's running an instruction equivalent to the LDIR instruction for the Z80. Here's a quote from the Z80 manual which explains the instruction's function: "This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the DE register pair. Both these register pairs are incremented and the BC (Byte Counter) register pair is decremented. If decrementing causes the BC to go to zero, the instruction is terminated. If BC is not zero, the program counter is decremented by two and the instruction is repeated." This instruction takes 23 states to fully execute. I've also written (microprogrammed) other instructions to test the processor's function: ADD,SUB, Boolian operations, LD, JP Z, Rotate/Shift, PUSH, POP, and a few others. So far, its been successful. I mainly just need to test the CALL, RET, and Interrupts to fully test the processor.
UPDATE Dec 09:
The Interrupt system and the Call and Return instructions all work correctly now. All implemeted instructions function correctly. I'm calling the design complete and it's ready to be built (see my latest blog entry for more info)!
Here is a diagram of the data path of the processor. It shows the data flow between the different elements.
IR = Instruction Register (16-Bit)
PC = Program Counter Register (16-Bit)
SP = Stack Pointer Register (16-Bit)
A-L = General Purpose Registers (8-Bit)
TMP A, B, 16 = Temporary Registers (not user accessible)
TRI = Tri-state buffers
ALU = Arithmetic Logic Unit
Here are the wire wrap boards that i'm going to use:
Last Updated December 2009
Contact: Tai Oliphant
Copyright © Tai Oliphant 2009